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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
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Peak Dio d e Recovery d V/ d t Test Circuit
Vishay Siliconix
D.U.T.
+
Circuit layout con s ideration s
? Low s tray inductance
? G round plane
? Low leakage inductance
current tran s former
-
+
-
-
+
R g
?
?
?
?
dV/dt controlled by R g
Driver s ame type a s D.U.T.
I S D controlled by duty factor “D”
D.U.T. - device under te s t
+
-
V DD
Driver gate drive
P.W.
Period
D=
P.W.
Period
V GS = 10 V a
D.U.T. l S D waveform
Rever s e
recovery
current
Body diode forward
current
dI/dt
D.U.T. V D S waveform
Diode recovery
Re-applied
dV/dt
V DD
voltage
Inductor current
Body diode forward drop
Ripple ≤ 5 %
I S D
Note
a. V GS = 5 V for logic level device s
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91267 .
S13-0171-Rev. D, 04-Feb-13
7
Document Number: 91267
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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